libethercat - an embeddable realtime EtherCAT-master library
Communicate with EtherCAT slaves attached to a Network interface.
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dc.h
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1
15/*
16 * This file is part of libethercat.
17 *
18 * libethercat is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU Lesser General Public
20 * License as published by the Free Software Foundation; either
21 * version 3 of the License, or (at your option) any later version.
22 *
23 * libethercat is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
26 * Lesser General Public License for more details.
27 *
28 * You should have received a copy of the GNU Lesser General Public
29 * License along with libethercat (LICENSE.LGPL-V3); if not, write
30 * to the Free Software Foundation, Inc., 51 Franklin Street, Fifth
31 * Floor, Boston, MA 02110-1301, USA.
32 *
33 * Please note that the use of the EtherCAT technology, the EtherCAT
34 * brand name and the EtherCAT logo is only permitted if the property
35 * rights of Beckhoff Automation GmbH are observed. For further
36 * information please contact Beckhoff Automation GmbH & Co. KG,
37 * Hülshorstweg 20, D-33415 Verl, Germany (www.beckhoff.com) or the
38 * EtherCAT Technology Group, Ostendstraße 196, D-90482 Nuremberg,
39 * Germany (ETG, www.ethercat.org).
40 *
41 */
42
43#ifndef LIBETHERCAT_DC_H
44#define LIBETHERCAT_DC_H
45
46#include <libosal/types.h>
47
48#include "libethercat/common.h"
49#include "libethercat/idx.h"
50#include "libethercat/pool.h"
52
53#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_ACTIVATION ( 0x01u )
54#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_SYNC0 ( 0x02u )
55#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_SYNC1 ( 0x04u )
56#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_AUTO_ACTIVATION ( 0x08u )
57#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_EXT_64BIT ( 0x10u )
58#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_START_TIME_CHECK ( 0x20u )
59#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_NEAR_FUTURE_CONFIG ( 0x40u )
60#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_DEBUG_PULSE ( 0x80u )
61
62#define EC_DC_ACTIVATION_REG_SYNC0 ( 0x3 )
63#define EC_DC_ACTIVATION_REG_SYNC1 ( 0x5 )
64#define EC_DC_ACTIVATION_REG_SYNC01 ( 0x7 )
65
66typedef struct ec_dc_info_slave {
67 int use_dc;
68 int next;
69 int prev;
70
71 osal_uint8_t available_ports;
72 osal_uint32_t receive_times[4];
73
74 osal_int32_t t_delay_childs;
75 osal_int32_t t_delay_with_childs;
76 osal_int32_t t_delay_slave;
77 osal_int32_t t_delay_parent_previous;
78
80 osal_uint32_t cycle_time_0;
81 osal_uint32_t cycle_time_1;
82 osal_int32_t cycle_shift;
84
85typedef enum ec_dc_mode {
86 dc_mode_master_clock = 0,
87 dc_mode_ref_clock,
88 dc_mode_master_as_ref_clock
89} ec_dc_mode_t;
90
91typedef struct ec_dc_info {
92 osal_uint16_t master_address;
93 int have_dc;
94 int next;
95 int prev;
96 int have_64bit;
97
98 osal_uint64_t dc_time;
99 osal_int64_t dc_sto;
100 osal_uint64_t rtc_time;
101 osal_int64_t rtc_sto;
102 osal_int64_t act_diff;
103 osal_uint64_t packet_duration;
104
106
107 struct {
108 double p_part;
109 double i_part;
110 double i_part_limit;
111
112 double kp;
113 double ki;
114 double kd;
116
117 osal_uint64_t sent_time_nsec;
118
119 ec_dc_mode_t mode;
120
123
124struct ec;
125
126#ifdef __cplusplus
127extern "C" {
128#endif
129
131
148int ec_dc_config(struct ec *pec);
149
151
166int ec_dc_sync(struct ec *pec, osal_uint16_t slave, osal_uint8_t dc_active,
167 osal_uint32_t cycle_time_0, osal_uint32_t cycle_time_1, osal_int32_t cycle_shift);
168
169#ifdef __cplusplus
170}
171#endif
172
173#endif // LIBETHERCAT_DC_H
174
ethercat master common stuff
ethercat datagram
int ec_dc_sync(struct ec *pec, osal_uint16_t slave, osal_uint8_t dc_active, osal_uint32_t cycle_time_0, osal_uint32_t cycle_time_1, osal_int32_t cycle_shift)
Configure EtherCAT slave for distributed clock sync0 and sync1 pulse.
int ec_dc_config(struct ec *pec)
Prepare EtherCAT master and slaves for distributed clocks.
ethercat index
Data pool implementation.
Definition datagram.h:89
Definition dc.h:66
int activation_reg
DC Sync Activation Register (0x981). 0x3 = Sync0, 0x5 = Sync1, 0x7 = Sync01.
Definition dc.h:79
int use_dc
flag, whether to use dc
Definition dc.h:67
osal_uint32_t cycle_time_1
cycle time of sync 1 [ns]
Definition dc.h:81
osal_uint32_t receive_times[4]
latched port receive times
Definition dc.h:72
osal_uint8_t available_ports
available ports for dc config
Definition dc.h:71
osal_uint32_t cycle_time_0
cycle time of sync 0 [ns]
Definition dc.h:80
osal_int32_t cycle_shift
cycle shift time [ns]
Definition dc.h:82
int prev
marker for previous dc slave
Definition dc.h:69
int next
marker for next dc slave
Definition dc.h:68
Definition dc.h:91
int have_dc
At least one slave is using DCs.
Definition dc.h:93
ec_cyclic_datagram_t cdg
DC cyclic datagram.
Definition dc.h:121
osal_uint64_t rtc_time
Time from realtime (EtherCAT master) clock.
Definition dc.h:100
double timer_correction
Correction value for EtherCAT master timer in [ns].
Definition dc.h:105
osal_int64_t dc_sto
System time offset of DC master clock.
Definition dc.h:99
osal_uint64_t dc_time
Time from DC master clock.
Definition dc.h:98
struct ec_dc_info::@6 control
PI-controller to adjust EtherCAT master timer value.
osal_int64_t rtc_sto
System time offset of realtime clock.
Definition dc.h:101
osal_int64_t act_diff
Actual difference of DC and RTC clock.
Definition dc.h:102
osal_uint64_t packet_duration
Packet duration on wire.
Definition dc.h:103
ethercat master structure
Definition ec.h:192