43#ifndef LIBETHERCAT_DC_H
44#define LIBETHERCAT_DC_H
46#include <libosal/types.h>
47#include <libosal/mutex.h>
54#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_ACTIVATION ( 0x01u )
55#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_SYNC0 ( 0x02u )
56#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_SYNC1 ( 0x04u )
57#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_AUTO_ACTIVATION ( 0x08u )
58#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_EXT_64BIT ( 0x10u )
59#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_START_TIME_CHECK ( 0x20u )
60#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_NEAR_FUTURE_CONFIG ( 0x40u )
61#define EC_REG_DCSYNCACT__SYNC_OUT_UNIT_DEBUG_PULSE ( 0x80u )
63#define EC_DC_ACTIVATION_REG_SYNC0 ( 0x3 )
64#define EC_DC_ACTIVATION_REG_SYNC1 ( 0x5 )
65#define EC_DC_ACTIVATION_REG_SYNC01 ( 0x7 )
75 osal_int32_t t_delay_childs;
76 osal_int32_t t_delay_with_childs;
77 osal_int32_t t_delay_slave;
78 osal_int32_t t_delay_parent_previous;
86typedef enum ec_dc_mode {
87 dc_mode_master_clock = 0,
89 dc_mode_master_as_ref_clock
93 osal_uint16_t master_address;
109 double diffsum_limit;
117 osal_uint64_t sent_time_nsec;
164void ec_dc_sync(
struct ec *pec, osal_uint16_t slave, osal_uint8_t dc_active,
165 osal_uint32_t cycle_time_0, osal_uint32_t cycle_time_1, osal_int32_t cycle_shift);
ethercat master common stuff
int ec_dc_config(struct ec *pec)
Prepare EtherCAT master and slaves for distributed clocks.
void ec_dc_sync(struct ec *pec, osal_uint16_t slave, osal_uint8_t dc_active, osal_uint32_t cycle_time_0, osal_uint32_t cycle_time_1, osal_int32_t cycle_shift)
Configure EtherCAT slave for distributed clock sync0 and sync1 pulse.
Data pool implementation.
int activation_reg
DC Sync Activation Register (0x981). 0x3 = Sync0, 0x5 = Sync1, 0x7 = Sync01.
Definition dc.h:80
int use_dc
flag, whether to use dc
Definition dc.h:68
osal_uint32_t cycle_time_1
cycle time of sync 1 [ns]
Definition dc.h:82
osal_uint32_t receive_times[4]
latched port receive times
Definition dc.h:73
osal_uint8_t available_ports
available ports for dc config
Definition dc.h:72
osal_uint32_t cycle_time_0
cycle time of sync 0 [ns]
Definition dc.h:81
osal_int32_t cycle_shift
cycle shift time [ns]
Definition dc.h:83
int prev
marker for previous dc slave
Definition dc.h:70
int next
marker for next dc slave
Definition dc.h:69
int have_dc
At least one slave is using DCs.
Definition dc.h:94
ec_cyclic_datagram_t cdg
DC cyclic datagram.
Definition dc.h:121
osal_uint64_t rtc_time
Time from realtime (EtherCAT master) clock.
Definition dc.h:100
double timer_correction
Correction value for EtherCAT master timer in [ns].
Definition dc.h:105
osal_int64_t dc_sto
System time offset of DC master clock.
Definition dc.h:99
osal_uint64_t dc_time
Time from DC master clock.
Definition dc.h:98
struct ec_dc_info::@6 control
PI-controller to adjust EtherCAT master timer value.
osal_int64_t rtc_sto
System time offset of realtime clock.
Definition dc.h:101
osal_int64_t act_diff
Actual difference of DC and RTC clock.
Definition dc.h:102
osal_uint64_t packet_duration
Packet duration on wire.
Definition dc.h:103
ethercat master structure
Definition ec.h:188