Registers

Data Structures
struct	ec_reg_dl_status

Macros
#define	EC_REG_TYPE   (0x0000u)
	Type.
#define	EC_REG_SM_FFMU_CH   (0x0004u)
	Sync manager and FMMU channels.
#define	EC_REG_FMMU_CH   (0x0004u)
	FMMU channels.
#define	EC_REG_SM_CH   (0x0005u)
	Sync manager channels.
#define	EC_REG_RAM_SIZE   (0x0006u)
	RAM size.
#define	EC_REG_PORTDES   (0x0007u)
	Port description.
#define	EC_REG_ESCSUP   (0x0008u)
	ESC support.
#define	EC_REG_ESCSUP__FMMU_BIT_OP_NOT_SUPP   (0x0001u)
	FMMU bit not supported in OP.
#define	EC_REG_ESCSUP__NO_SUPP_RESERVED_REG   (0x0002u)
	Reserver regs not supported.
#define	EC_REG_ESCSUP__DC_SUPP   (0x0004u)
	Distributed clock support.
#define	EC_REG_ESCSUP__DC_RANGE   (0x0008u)
	Distributed clock 64-bit support.
#define	EC_REG_ESCSUP__LOW_J_EBUS   (0x0010u)
	Low jitter on EBUS.
#define	EC_REG_ESCSUP__ENH_LD_EBUS   (0x0020u)
	Enhanced link detection on EBUS.
#define	EC_REG_ESCSUP__ENH_LD_MII   (0x0040u)
	Enhanced link detection on MII.
#define	EC_REG_ESCSUP__FCS_S_ERR   (0x0080u)
	Frame checksum error counter.
#define	EC_REG_ESCSUP__ENHANCED_DC_SYNC_ACT   (0x0100u)
	Enhanced distributed clock sync activation.
#define	EC_REG_ESCSUP__NOT_SUPP_LRW   (0x0200u)
	LRW not supported.
#define	EC_REG_ESCSUP__NOT_SUPP_BAFRW   (0x0400u)
	BAFRW not supporte.
#define	EC_REG_ESCSUP__S_FMMU_SYMC   (0x0800u)
	FMMU sync.
#define	EC_REG_STADR   (0x0010u)
	Station address.
#define	EC_REG_ALIAS   (0x0012u)
	Station alias.
#define	EC_REG_DLCTL   (0x0100u)
	Data-link-layer control.
#define	EC_REG_DLPORT   (0x0101u)
	Data-link-layer port.
#define	EC_REG_DLALIAS   (0x0103u)
	Data-link-layer alias.
#define	EC_REG_DLSTAT   (0x0110u)
	Data-link-layer status.
#define	EC_REG_ALCTL   (0x0120u)
	Application-layer control.
#define	EC_REG_ALSTAT   (0x0130u)
	Application-layer status.
#define	EC_REG_ALSTATCODE   (0x0134u)
	Application-layer status code.
#define	EC_REG_PDICTL   (0x0140u)
	PDI control.
#define	EC_REG_IRQMASK   (0x0200u)
	IRQ mask.
#define	EC_REG_RXERR   (0x0300u)
	RX error.
#define	EC_REG_EEPCFG   (0x0500u)
	EEPROM config.
#define	EC_REG_EEPCTL   (0x0502u)
	EEPROM control.
#define	EC_REG_EEPSTAT   (0x0502u)
	EEPROM status.
#define	EC_REG_EEPADR   (0x0504u)
	EEPROM address.
#define	EC_REG_EEPDAT   (0x0508u)
	EEPROM data.
#define	EC_REG_MII_CTRLSTAT   (0x0510u)
	MII control/status.
#define	EC_REG_MII_PHY_ADR   (0x0512u)
	MII phy address.
#define	EC_REG_MII_PHY_REG   (0x0513u)
	MII phy register.
#define	EC_REG_MII_PHY_DATA   (0x0514u)
	MII phy data.
#define	EC_REG_MII_ECAT_ACC   (0x0516u)
	MII ECAT ACC.
#define	EC_REG_MII_PDI_ACC   (0x0517u)
	MII PDI ACC.
#define	EC_REG_MII_PHY0_ST   (0x0518u)
	MII phy0 status.
#define	EC_REG_MII_PHY1_ST   (0x0519u)
	MII phy1 status.
#define	EC_REG_MII_PHY2_ST   (0x051Au)
	MII phy2 status.
#define	EC_REG_MII_PHY3_ST   (0x051Bu)
	MII phy3 status.
#define	EC_REG_FMMU0   (0x0600u)
	FMMU0 base.
#define	EC_REG_FMMU1   (EC_REG_FMMU0 + 0x10u)
	FMMU1 base.
#define	EC_REG_FMMU2   (EC_REG_FMMU1 + 0x10u)
	FMMU2 base.
#define	EC_REG_FMMU3   (EC_REG_FMMU2 + 0x10u)
	FMMU3 base.
#define	EC_REG_SM0   (0x0800u)
	Sync manager 0 base.
#define	EC_REG_SM1   (EC_REG_SM0 + 0x08u)
	Sync manager 1 base.
#define	EC_REG_SM2   (EC_REG_SM1 + 0x08u)
	Sync manager 2 base.
#define	EC_REG_SM3   (EC_REG_SM2 + 0x08u)
	Sync manager 3 base.
#define	EC_REG_SM0STAT   (EC_REG_SM0 + 0x05u)
	Sync manager 0 status.
#define	EC_REG_SM0ACT   (EC_REG_SM0 + 0x06u)
	Sync manager 0 active.
#define	EC_REG_SM0CONTR   (EC_REG_SM0 + 0x07u)
	Sync manager 0 control.
#define	EC_REG_SM1STAT   (EC_REG_SM1 + 0x05u)
	Sync manager 1 status.
#define	EC_REG_SM1ACT   (EC_REG_SM1 + 0x06u)
	Sync manager 1 active.
#define	EC_REG_SM1CONTR   (EC_REG_SM1 + 0x07u)
	Sync manager 1 control.
#define	EC_REG_DCTIME0   (0x0900u)
	Distributed clock port time 0.
#define	EC_REG_DCTIME1   (0x0904u)
	Distributed clock port time 1.
#define	EC_REG_DCTIME2   (0x0908u)
	Distributed clock port time 2.
#define	EC_REG_DCTIME3   (0x090Cu)
	Distributed clock port time 3.
#define	EC_REG_DCSYSTIME   (0x0910u)
	Distributed clock system time.
#define	EC_REG_DCSOF   (0x0918u)
	Distributed clock offset.
#define	EC_REG_DCSYSOFFSET   (0x0920u)
	Distributed clock system time offset.
#define	EC_REG_DCSYSDELAY   (0x0928u)
	Distributed clock system time delay.
#define	EC_REG_DCSYSDIFF   (0x092Cu)
	Distributed clock system time difference.
#define	EC_REG_DCSPEEDCNT   (0x0930u)
	Distributed clock speed count.
#define	EC_REG_DCTIMEFILT   (0x0934u)
	Distributed clock time filter.
#define	EC_REG_DCCUC   (0x0980u)
	Distributed clock CUC.
#define	EC_REG_DCSYNCACT   (0x0981u)
	Distributed clock sync activation.
#define	EC_REG_DCSTART0   (0x0990u)
	Distributed clock start time.
#define	EC_REG_DCCYCLE0   (0x09A0u)
	Distributed clock Sync0 cycletime.
#define	EC_REG_DCCYCLE1   (0x09A4u)
	Distributed clock Sync1 cycletime.

Typedefs
typedef struct ec_reg_dl_status	ec_reg_dl_status_t
	DL status register type.

Enumerations
enum	{   EC_CMD_NOP = 0x00 , EC_CMD_APRD = 0x01 , EC_CMD_APWR = 0x02 , EC_CMD_APRW = 0x03 ,   EC_CMD_FPRD = 0x04 , EC_CMD_FPWR = 0x05 , EC_CMD_FPRW = 0x06 , EC_CMD_BRD = 0x07 ,   EC_CMD_BWR = 0x08 , EC_CMD_BRW = 0x09 , EC_CMD_LRD = 0x0A , EC_CMD_LWR = 0x0B ,   EC_CMD_LRW = 0x0C , EC_CMD_ARMW = 0x0D , EC_CMD_FRMW = 0x0E }

Detailed Description

This modules contains EtherCAT register defines.

Enumeration Type Documentation

anonymous enum

anonymous enum

Ethercat registers

Enumerator
EC_CMD_NOP	no op
EC_CMD_APRD	auto increment read
EC_CMD_APWR	auto increment write
EC_CMD_APRW	auto increment read write
EC_CMD_FPRD	configured address read
EC_CMD_FPWR	configured address write
EC_CMD_FPRW	configured address read write
EC_CMD_BRD	broadcast read
EC_CMD_BWR	broaddcast write
EC_CMD_BRW	broadcast read write
EC_CMD_LRD	logical memory read
EC_CMD_LWR	logical memory write
EC_CMD_LRW	logical memory read write
EC_CMD_ARMW	auto increment read mulitple write
EC_CMD_FRMW	configured read mulitple write